Field of Invention
The invention generally relates to a phase interpolator; more particularly, the invention relates to a phase interpolator and a clock and data recovery circuit using the same, so as to obtain a wide operation frequency range without reducing the maximum operation speed due to parasitic capacitive effects.
Description of Prior Art
Clock and data recovery (CDR) circuits are generally used to sample an input data signal, extract the clock from the input data signal, and retime the sampled data in the receiver. In a conventional CDR circuit, a phase interpolator for adjusting the phase of the sampling clock is frequently employed.
Since the operation frequency range and the operation speed of the receiver are critically affected by circuit characteristics of the phase interpolator, designer may need more time to develop a trade-off between the operation frequency range and the operation speed, whereas it is rather difficult to ensure the performance of both.
For example, in a conventional phase interpolator design, the operation frequency range can be increased by additionally arranging a switch capacitor array (SCA) at an output terminal. However, the effective capacitance at the output terminal of the phase interpolator may be increased because of parasitic capacitance caused by the SCA, and thus the maximum operation speed of the phase interpolator may be reduced.